Reduced-Stress Through-Chip Feature and Method of Making the Same

ABSTRACT

A feature is inscribed in a major surface of a microelectronic workpiece having a material property expressed as a reference coefficient value. The feature includes a first material having a first coefficient value for the material property and a second material having a second coefficient value for the material property. The first coefficient value is different from the reference coefficient value different from the first coefficient value and the second coefficient value is different from the first coefficient value. The first and second materials behave as an aggregate having an aggregate coefficient value for the material property between the first coefficient value and the reference coefficient value.

TECHNICAL FIELD

The present invention relates generally to electronic components and inparticular embodiments to a reduced-stress through-chip feature andmethod of making the same.

BACKGROUND

Features inscribed into or provided through the surface of asemiconductor wafer or other microelectronic workpiece can serve avariety of functions. For example, a “via” or a “vertical interconnectaccess” is a through-chip feature that electrically couple terminals orother conductive elements on or proximate to one side of a wafer toconductive elements on or proximate to the other side of the wafer.

Typically, the formation of a via involves providing an opening in themicroelectronic workpiece, i.e., in the wafer of semiconductor material.These openings can be manufactured in different ways, such as by using adry-etch method or laser-drilling. Next, the wall or inner surface ofthe opening is electrically passivated by a layer of a dielectric, i.e.,a non-conductive, material. This layer also serves as a seed layerenhancing adherence of other materials to the surface. Finally, theopening, which is now lined with the seed layer, is typically filledcompletely with a conductive material, such as a metal like copper,aluminum, tungsten or the like.

This approach, however, has certain drawbacks. First, the development ofvoids or cavities inside the conductive material caused by the shrinkageof the material during the solidification of the material cannot becompletely prevented. Moreover, the mismatch of material properties suchas the respective coefficients of thermal expansion (CTE) between theconductive material and the semiconductor substrate leads to differentmagnitudes of expansion as the microelectronic device or workpieceundergoes a temperature change. The mechanical stresses generatedthereby may lead to cracks in and potentially a failure of themicroelectronic device or workpiece.

Accordingly, a need exists for a through-chip feature that does notmanifest these drawbacks. Furthermore a need exists for a method offorming such features.

SUMMARY OF THE INVENTION

An aspect of the present invention is the deposition of an aggregate ofelements that are heterogeneous at least with respect to their expansionbehavior. An aggregate, as used herein, shall mean a formation of aplurality of materials, heterogeneous at least as to one materialproperty, such as CTE.

In an embodiment of the present invention, an inscribed feature isprovided in a major surface of a microelectronic workpiece such as asemiconductor wafer, the feature having the above-described aggregatedisposed therein.

In another embodiment of the present invention, a feature, such as anopening in a semiconductor wafer is formed of a first material having afirst CTE deposited on the wafer, which subsequently is either coveredby or filled with at least one additional layer of a material having asecond CTE different from the first. The material of the additionallayer or fill may be selected with a view to compensating, orcounterbalancing, the thermal expansion or shrinkage of the firstmaterial. Moreover, the feature may thus be provided with at least onemeans for counteracting any CTE mismatch between the first material andthe semiconductor wafer, in order to at least decrease (or, ideally,even neutralize) the stress-inducing effect of the difference inexpansion behavior between the interconnect and the bulk semiconductormaterial.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings,

FIG. 1 shows the relationship between the thickness of an interconnectlayer and the diameter of a dielectric compensation element disposedtherein; and

FIG. 2 shows an example of an interconnect formed of an aggregate.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent invention provides many applicable inventive concepts that canbe embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not limit the scope of the invention.

The expansion behavior of an element, e.g., a hollow cylinder formed,for example, in a layer of material, is governed by the coefficient ofthermal expansion (CTE) of its material and its thickness. The sameapplies for an element completely filling an opening, with the provisionthat the characteristic length defining the absolute value of expansionor shrinkage (i.e., negative expansion) is its diameter, not thickness.While the CTE defines the relative expansion (or shrinkage) of thematerial when subjected to a given temperature change, the thickness ofsuch a layer (or diameter of such solid filling) makes it possible todetermine the absolute value of such expansion (or shrinkage) for acertain element.

In an exemplary embodiment, a feature such as an interconnect is to beformed in a semiconductor substrate of silicon, having a CTE of about3·10⁻⁶ K⁻¹. Due to its high electrical conductivity, copper (having aCTE of about 16·10⁻⁶ K⁻¹) is often chosen as the conductive material forforming the interconnect. If the opening in the semiconductor materialwas completely filled with copper, then the difference in the CTE ofboth materials would generate a strong in-plane stress in amicroelectronic device having such interconnect. This stress can easilydamage or destroy the device. It can be shown, however, that by formingan aggregate having a plurality of CTE values, an overall CTE of theinterconnect and the additional layer or layers and/or fill can bereached which is significantly closer to the CTE of the semiconductormaterial than the CTE of known interconnects. This relationship is shownin FIG. 1.

For a given thickness x_(C) and CTE α_(C) of a conductive layerconstituting an interconnect in an opening of a semiconductor with a CTEα_(SC), the diameter x_(D) of a dielectric fill with CTE α_(D) iscalculated as:

$x_{D} = {\frac{\alpha_{SC} - \alpha_{C}}{\alpha_{D} - \alpha_{SC}} \cdot x_{C}}$

So, the x_(D):x_(C) ratio for a balanced expansion behavior of bulksemiconductor material versus the filling of the opening (i.e., theinterconnect layer plus the dielectric filling) is calculated as:

$\frac{x_{D}}{x_{C}} = \frac{\alpha_{SC} - \alpha_{C}}{\alpha_{D} - \alpha_{SC}}$

In the above example, let the dielectric fill of the conductive layerconstituting the interconnect be silicon oxide, having a CTE α_(D) ofabout 0.65·10⁻⁶ K⁻¹. Then the diameter x_(D) of the fill would have tobe about five times the thickness x_(C) of the conductive layer to reachan overall expansion behavior of the conductive layer and dielectricfill that matches the expansion behavior of the semiconductor material.As an example, a copper layer of about 200 nm in thickness would requirea silicon oxide filling of about 1106 nm in diameter to reach fullcompensation. However, even if the actual x_(D):x_(C) ratio is notexactly the same as calculated above, a significant decrease of in-planestress can still be achieved.

Referring now to FIG. 2, an exemplary embodiment of an interconnect isshown.

In a semiconductor substrate 1, for instance a silicon wafer comprisinga multitude of integrated circuit chips, a blind hole 2 is manufactured,for instance in a dry etch process. A seed layer 3, e.g., a dielectricseed layer, is deposited on the inner walls of the blind hole 2. Theseed layer 3 is then covered with a layer of a conductive material 4.Finally, the inner surface of the conductive layer 4 is filled with anon-conductive material 5.

When the CTE and the relative thicknesses of both the conductive layer 4and the non-conductive layer 5 are selected so as to approach that ofthe substrate material, the aggregate of elements filling the blind hole2 behaves approximately like the semiconductor material of the substrate1. Thermal stress in the substrate 1 caused by the CTE mismatch betweenthe semiconductor material of the substrate 1 and the through-waferinterconnect is therefore considerably lower than with a conventionalvia under the same thermal conditions.

The non-conductive layer 5 can be an oxide, nitride or carbide ofsilicon, an oxide, nitride or carbide of titanium, an oxide, nitride orcarbide of ruthenium, or an oxide, nitride or carbide of aluminum, asexamples. In one particular example, the non-conductive layer 5comprises SiO₂ precipitated from gaseous SiO₄C₈H₂O(Tetraethylorthosilicate, TEO).

In another embodiment, a third material (not shown) can be deposited inthe opening 2. In various embodiments, the third material can be anoxide, nitride or carbide of silicon, an oxide, nitride or carbide oftitanium, an oxide, nitride or carbide of ruthenium, or an oxide,nitride or carbide of aluminum.

In a subsequent step, the substrate 1 may be thinned by removingsemiconductor material from its underside. If enough material isremoved, for instance in a grinding process, then the lower end of theaggregate of elements 3, 4, 5 filling the blind hole 2 is exposed suchthat the conductive layer 4 forms an electrically conductivethrough-wafer interconnect.

Furthermore, the workpiece, for instance the wafer carrying integratedcircuits, may be diced, thus singulating the individual chips, which maythen be used in a semiconductor device, for instance in a so-calledpackage.

While this invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications and combinations of theillustrative embodiments, as well as other embodiments of the invention,will be apparent to persons skilled in the art upon reference to thedescription. It is therefore intended that the appended claims encompassany such modifications or embodiments.

1. In a microelectronic workpiece having a major surface, a material property expressed as a reference coefficient value, the microelectronic workpiece having a feature inscribed in the major surface, the feature comprising: a first material having a first coefficient value for the material property, the first coefficient value being different from the reference coefficient value; a second material having a second coefficient value for the material property different from the first coefficient value; wherein the first and second materials behave as an aggregate having an aggregate coefficient value for the material property between the first coefficient value and the reference coefficient value.
 2. The microelectronic workpiece of claim 1, wherein the reference, first and second coefficient values are coefficients of thermal expansion.
 3. The microelectronic workpiece of claim 2, wherein the feature is an electrically conductive interconnect.
 4. The microelectronic workpiece of claim 3, wherein the first material is a conductive material.
 5. The microelectronic workpiece of claim 4, wherein the second material comprises a dielectric.
 6. The microelectronic workpiece of claim 2, wherein the first and second material are in thermal contact within the inscribed feature.
 7. The microelectronic workpiece of claim 6, wherein the first and second materials, as an aggregate, have a coefficient of thermal expansion approximately equal to the reference coefficient value.
 8. A semiconductor device comprising: a semiconductor substrate; active circuitry disposed at an upper surface of the semiconductor substrate; a through-via hole extending from the upper surface to a lower surface of the semiconductor substrate; an electrically conductive material lining the through-via hole; and an electrically insulating material filling the through-via hole such that the electrically conductive material is disposed between the insulating material and the semiconductor substrate.
 9. The device of claim 8, wherein the electrically conductive material comprises copper.
 10. The device of claim 9, wherein the electrically insulating material comprises silicon oxide.
 11. The device of claim 8, wherein the electrically conductive material has a thickness XD and the electrically insulating material has a diameter x_(C), wherein x_(D):x_(C) is set so that $\frac{x_{D}}{x_{C}} \cong \frac{\alpha_{SC} - \alpha_{C}}{\alpha_{D} - \alpha_{SC}}$ wherein the semiconductor substrate has a coefficient of thermal expansion (CTE) α_(SC), the electrically conductive material has a CTE ac, and the electrically insulating material has a CTE α_(D).
 12. The device of claim 8, wherein the semiconductor substrate has a coefficient of thermal expansion (CTE), the electrically conductive material has a CTE, and the electrically insulating material has a CTE, wherein the electrically conductive material and the electrically insulating material have a net CTE that is between the CTE of the semiconductor substrate and the CTE of the electrically conductive material.
 13. A method for forming an electrically conductive interconnect in a semiconductor substrate having a reference coefficient of thermal expansion, the method comprising: forming an opening in at least one surface of the substrate; partially filling the opening with a first material having a first coefficient of thermal expansion different from the reference coefficient; at least partially filling the opening with a second material, the second material having a second coefficient of thermal expansion different from the first coefficient, wherein the first and second materials behave as an aggregate having a net coefficient of thermal expansion between the first coefficient and the reference coefficient.
 14. The method of claim 13, further comprising forming a seed layer on an inner surface of the opening before partially filling the opening with the first material.
 15. The method of claim 14, wherein forming the seed layer comprises depositing a dielectric material.
 16. The method of claim 13, wherein partially filling the opening with the first material comprises depositing a conductive material.
 17. The method of claim 13, wherein the second material and thickness of the second material are selected so as to reduce an effect that otherwise would be caused by the difference between the coefficients of thermal expansion of the semiconductor substrate and the first material.
 18. The method of claim 13, wherein the second material comprises an oxide, nitride or carbide of silicon.
 19. The method of claim 18, wherein the second material comprises SiO₂ precipitated from gaseous SiO₄C₈H₂₀ (Tetraethylorthosilicate, TEO).
 20. The method of claim 13, wherein the second material comprises an oxide, nitride or carbide of titanium.
 21. The method of claim 13, wherein the second material comprises an oxide, nitride or carbide of ruthenium.
 22. The method of claim 13, wherein the second material comprises an oxide, nitride or carbide of aluminum.
 23. The method of claim 13, further comprising depositing a third material in the opening, the third material comprising an oxide, nitride or carbide of silicon.
 24. The method of claim 13, further comprising depositing a third material in the opening, the third material comprising an oxide, nitride or carbide of titanium.
 25. The method of claim 13, further comprising depositing a third material in the opening, the third material comprising an oxide, nitride or carbide of ruthenium.
 26. The method of claim 13, further comprising depositing a third material in the opening, the third material comprising an oxide, nitride or carbide of aluminum. 